1. Field of the Invention
The present invention generally relates to successive approximation A/D converters, and particularly relates to a successive approximation A/D converter utilizing a switched capacitor D/A converter.
2. Description of the Related Art
Successive approximation A/D converters can be implemented by use of relatively simple circuit configurations, and can be manufactured at relatively low cost due to their suitability for CMOS process while providing moderate conversion time and moderate conversion accuracy. This is why successive approximation A/D converters are used in a variety of fields. FIG. 1 is a drawing showing a differential switched capacitor DAC used in a related-art charge redistribution A/D converter, which is a representative configuration of the successive approximation A/D converter. Patent Document 1 discloses a similar circuit.
In the following, the configuration and operation of the circuit shown in FIG. 1 will be described briefly. The circuit of FIG. 1 includes switches SW1 through SW14, capacitors C1 through C12, and a comparator COMP1. VIN+ indicates a plus-side analog input (+) and VIN− indicates a minus-side analog input (−), together forming differential inputs. Furthermore, TOP+ designates a plus-side top plate of a capacitor array, and TOP− designates a minus-side top plate of the capacitor array. Vref+ is a plus-side reference potential (5V), and Vref− is a minus-side reference potential (0V). GND is the potential (2.5V) of the signal ground of this circuit. Furthermore, VCM2 is a bias potential applied to the top plate at the time of sampling, and COUT1 is the output of the comparator.
Capacitors C1 through C6 have relative capacitances 1C, 1C, 2C, 4C, 8C, and 16C, respectively. By the same token, capacitors C7 through C12 have relative capacitances 1C, 1C, 2C, 4C, 8C, and 16C, respectively.
The positions of the switches illustrated in FIG. 1 show their positions at the time of sampling. At the time of sampling, the potential VIN+ is charged in capacitors C1 through C6, and the potential VIN− is charged in capacitors C7 through C12. After the end of the sampling, switches SW13 and SW14 are opened, and the switches SW1 through SW12 are manipulated. Through the manipulation of the switches SW1 through SW12, the potential at the bottom plates of the capacitors C1 through C12 (i.e., these ends of the capacitors connected to the switches SW1 through SW12) are selectively set to either one of Vref+, Vref−, and GND.
In the following, a description will be given of the plus-side as a concrete example. At the time of sampling, all of the capacitors C1 through C6 are charged to the analog input potential VIN+. After the sampling, the switch SW13 is opened to place TOP+ in a floating state. Then, the capacitors C1 through C5 are coupled to GND through the switches SW1 through SW5, respectively, and the capacitor C6 is coupled to the reference potential Vref+ through the switch SW6, for example. Through these couplings, charge accumulated by the input potential VIN+ at the time of sampling is redistributed between the sampling capacitors C1 through C6, resulting in the potential of TOP+ being ((Vref+)−GND)/2−VIN+. Namely, in this case, the voltage between Vref+ and GND is divided by half by a capacitance of 16C of the capacitor C6 and a capacitance of 16C that is the total capacitance of the capacitors C1 through C5. The input potential VIN+ is then subtracted from the divided potential to generate the potential of TOP+.
Manipulating the couplings of the switches SW1 through SW6 makes it possible to change a ratio by which the voltage between Vref+ and GND is divided by capacitors, thereby adjusting the potential of TOP+. The same applies in the case of the minus-side. Manipulating the couplings of the switches SW7 through SW12 makes it possible to change a ratio by which the voltage between Vref− and GND is divided by capacitors, thereby adjusting the potential of TOP−. The comparator COMP1 receives the potential of TOP+ and the potential of TOP− as inputs thereof, and generates the output COUT1 responsive to a difference between the two potentials. Couplings of the switches SW1 through SW12 are successively changed according to the output COUT1, thereby controlling the couplings of the switches until a desired output is obtained. With this provision, a digital code (the state of the switches) corresponding to the difference between the analog input potentials VIN+ and VIN− is searched for through the control that is based on the output COUT1.
FIG. 2 is a drawing showing another circuit example of a successive approximation A/D converter. In FIG. 2, the same elements as those of FIG. 1 are referred to by the same numerals, and a description thereof will be omitted.
In the circuit configuration shown in FIG. 2, an amplifier AMP1 is provided on the input side. The amplifier AMP1 amplifies the analog input potentials VIN+ and VIN− to produce amplified potentials IVINP and IVINN. The amplified potentials IVINP and IVINN are then sampled by the capacitor array, thereby performing an A/D conversion operation the same as previously described. The use of the circuit configuration shown in FIG. 2 makes it possible to achieve a faster sampling speed by charging the capacitors C1 through C12 through the amplifier AMP1 at the time of sampling.
Successive approximation A/D converters can achieve moderate conversion time and moderate conversion accuracy, and are applicable to a wide variety of fields. In the application fields where higher speed (higher sampling rate) and lower power consumption are required, pipeline A/D converters are employed. The pipeline A/D converters use a sample-hold amplifier circuit for sampling an analog signal for the purpose of achieving a higher sampling rate.
FIG. 3 is a drawing showing an example of the configuration of a related-art sample-hold amplifier circuit. Non-Patent Document 3 discloses a similar circuit.
The circuit shown in FIG. 3 includes switches SW15 through SW23, capacitors C13 through C16, and an amplifier AMP2. VIN+ indicates a plus-side analog input and VIN− indicates a minus-side analog input. VOP is a plus-side output, and VON is a minus-side output. Moreover, NODE1 through NODE4 indicate internal nodes. Furthermore, BIAS1 is the bias potential of the bottom plate of the capacitors C15 and C16 at the time of sampling.
The positions of the switches illustrated in FIG. 3 show their positions at the time of sampling. At the time of sampling, the potential VIN+ is charged in the capacitor C13, and the potential VIN− is charged in the capacitor C14. In the hold state, the switches SW18, SW19, SW20, and SW21 are opened, and the switches SW17, SW22, and SW23 are closed. With this provision, the part of the charge stored in the capacitors C13 and C14 that corresponds to the potential difference between VIN+ and VIN− is transferred to the capacitors C15 and C16, so that the potential difference between VIN+ and VIN− is output as a plus-side output VOP and a minus-side output VON.
By use of a sample-hold amplifier circuit as shown in FIG. 3, pipeline A/D converters achieve high-speed sampling operations.
There has been an attempt to make a circuit configuration that incorporates the function of a sample-hold amplifier into a successive approximation A/D converter. FIG. 4 is a drawing showing an example of a successive approximation A/D converter in which the function of a sample-hold amplifier is incorporated (see Patent Document 2).
The circuit shown in FIG. 4 includes switches SW24 through SW26, capacitors C17 through C24, and amplifiers AMP3 and AMP4. VIN is an analog input, and COUT2 is the output of the comparator. NODE5 through NODE7 indicate internal nodes. BOT1 through BOT5 are the bottom plates of capacitors. Moreover, Vdd/2 corresponds to half the potential of the power supply voltage. In the same manner as in FIG. 1 and FIG. 2, the value of nC (n is an integer) provided in the drawing beside the capacitors C17 through C24 indicates the relative size of each capacitor.
In the circuit of FIG. 4, the inverting amplification circuit comprised of the capacitors C17 and C18 and the amplifier AMP3 functions as a sample-hold amplifier circuit. The provision of this circuit portion eliminates the need to charge the capacitors of the switched capacitor DAC comprised of the capacitors C19 through C24 directly by the analog input signal. Through reduction in the capacitance of the capacitor C17, it is possible to make such a design that the input capacitance as viewed from VIN is small. This brings about an advantage of high-speed sampling.
As the miniaturization of circuits is further advanced, there is an increasing demand to implement CMOS digital circuits and CMOS analog circuits on the same chip. It is required to integrate, at as low cost as possible, the CMOS analog circuits achieving high performance that matches the high-speed performance of the fine CMOS digital circuits.
In this context, there is also an increasing demand to make faster the successive approximation A/D converters that achieve moderate conversion time and moderate conversion accuracy with small circuit size at low cost. In order to make successive approximation A/D converters faster, it is vital to increase the speed of a check performed at the comparator and to shorten the sampling time.
In the related-art configuration as shown in FIG. 1, however, the sampling capacitors are charged by use of the external analog input signals, so that the sampling time is limited by the capacitance of the sampling capacitors. It is thus difficult to shorten the sampling time sufficiently. In the related-art configuration as shown in FIG. 2, it is possible to increase the speed of sampling by charging the capacitors through a buffer amplifier at the time of sampling. It is not possible, however, to sample an input signal that falls outside the range of the output signal of the buffer amplifier. In the most typical circuit configuration, the voltage gain of the buffer amplifier would be 1. In this case, the application of an input signal having a voltage equal to the power supply voltage does not produce the output signal of the buffer amplifier that has amplitude equal to the power supply voltage. The output signal will become slightly smaller than the power supply voltage. Because of this, it is not possible to perform a proper A/D conversion when an input signal has an amplitude equal to the power supply voltage.
Like the related-art circuit shown in FIG. 2, the related-art sample-hold amplifier circuit shown in FIG. 3 functions as a buffer amplifier for analog input signals, thereby achieving higher sampling speed. Non-Patent Document 3 discloses an example of application to the pipeline A/D converter, but stops short of describing configuration, problems, solution that become issues when application to the successive approximation A/D converter is considered.
Patent Document 2 that discloses the related-art circuit shown in FIG. 4 only shows an amplifier whose voltage gain is equal to 1. As in the case of the related-art circuit shown in FIG. 2, Patent Document 2 stops short of describing the problems and solutions associated with the A/D conversion of signal inputs having an amplitude equal to the power supply voltage. Further, only the circuit configuration of a single-ended switched-capacitor buffer amplifier is disclosed. No example is given of application to a differential circuit that is advantageous against the noise generated by digital circuits in the system LSI.
[Patent Document 1] U.S. Pat. No. 4,803,462
[Patent Document 2] Japanese Patent Application Publication No. 10-336033
[Non-Patent Document 1] R. K. Hester et al., “Fully Differential ADC with Rail-to-Rail Common-Mode Range and Nonlinear Capacitor Compensation,” IEEE Journal of Solid-State Circuits, Vol. 25, No.1, pp. 173–183, February 1990.
[Non-Patent Document 2] G. Promitzer, “12-bit Low-Power Fully Differential Switched Capacitor Noncalibrating Successive Approximation ADC with 1 MS/s,” IEEE Journal of Solid-StateCircuits, Vol. 36, No.7, pp. 1138–1143, July 2001.
[Non-Patent Document 3] L. A. Singer et al. and “A14-Bit10-MHz Calibration-Free CMOS Pipelined A/D Converter” Symposium on VLSI Circuits, pp. 94–95, 1996.
Accordingly, there is a need for a successive approximation A/D converter that can perform A/D conversion on input signals having an amplitude equal to the power supply voltage, and that is provided with a sample-hold amplifier circuit for shortening the sampling time.
Further, there is a need for a specific circuit configuration of the above-noted sample-hold amplifier circuit.
Moreover, there is a need for a double-stage D/A converter that is suitable for the above-noted successive approximation A/D converter.